The engineer's definitive guide to CEA manufacturing — from DFM/DFA best practices and cost optimization to selecting the right contract manufacturer for your PCB project.
Contract Electronic Assembly (CEA) is the outsourcing of PCB and electronic product manufacturing to a specialized third-party facility. Rather than building and staffing your own SMT line, wave solder equipment, and test rigs, you engage a contract manufacturer (CM) who already owns that infrastructure.
For startups and mid-size hardware companies, CEA unlocks access to precision manufacturing — 01005 component placement, BGA rework, X-ray inspection — that would cost millions to replicate in-house.
CEA spans everything from bare PCB assembly (PCBA) to full box-build, cable harness integration, firmware flashing, functional test, and drop-ship logistics.
EMS (Electronics Manufacturing Services) handles assembly only. A CEM (Contract Electronics Manufacturer) may own design input too. An ODM designs and builds to your spec. Know which model your partner operates under before signing.
Turnkey: the CM sources all components, manages the BOM, and delivers finished boards. Consignment: you supply parts and the CM assembles. Partial-turnkey is a hybrid — you provide unique or long-lead parts, CM sources the rest.
IPC-A-610 defines workmanship acceptance criteria. Class 1 = general electronics; Class 2 = industrial; Class 3 = aerospace/medical. Specify your class before quoting — it directly impacts price and lead time.
Offshore CMs (China, SE Asia) offer 40–60% lower labor cost but longer lead times, IP risk, and higher NRE for small volumes. Near-shore (Mexico, Eastern Europe) balances cost with supply chain visibility. Domestic is best for fast iterations or classified designs.
Understanding each stage helps you design for manufacturability and communicate clearly with your CM.
Industry-standard rules every PCB designer should know before sending files to a contract manufacturer.
Minimum trace width for 1oz copper: 0.1mm. Pad-to-pad clearance (SMD): 0.15mm min. Via annular ring ≥ 0.15mm. Tighter values require premium pricing and extended DRC review.
Use 0.05–0.1mm solder mask expansion on SMT pads. NSMD (non-solder-mask-defined) land patterns are preferred for BGAs <0.8mm pitch — they allow more copper for the solder joint.
Place at least 3 fiducials per board panel — and per side if double-sided SMT. Use 1mm copper circle with 3mm clear courtyard. Without fiducials, pick-and-place alignment degrades, especially above 500 ppm.
Design boards for V-score or tab-routed panel arrays. Leave ≥ 5mm rail width. Tab diameter ≥ 0.8mm, ≥ 3 tabs per edge. Panels increase throughput — critical for volumes >500 units.
For BGA pitch < 0.8mm, confirm CM has X-ray capability and SPI (solder paste inspection). Request first-article X-ray images. Via-in-pad requires filling and planarization — add NRE cost accordingly.
Supply Gerber X2 (or RS-274X) with embedded layer info. Include: drill file (Excellon), IPC-2581 netlist, BOMs with MPN+quantity, centroid/XY file, assembly drawings (PDF). Never compress stack-ups without documentation.
Align all polarized components (diodes, electrolytic caps, ICs) in the same direction. Consistent orientation reduces manual inspection time and eliminates a common assembly error. Reference IPC-7351B for standard orientations.
Maintain ≥ 0.2mm courtyard clearance between components for nozzle access. For wave solder, keep SMD components ≥ 5mm from THT components to prevent shadowing and cold joints.
Keep tall components (electrolytics, connectors) away from board edges to avoid nozzle collisions. For rework access, leave ≥ 2mm clearance around BGAs and QFNs on all sides.
Every unique component requires a separate feeder. Consolidate resistor/cap values (e.g. use 10k instead of 9.1k where tolerance allows). Each unique MPN adds $15–50/run in setup cost.
Balance thermal exposure on 0402 and smaller passives — asymmetric land patterns cause tombstoning during reflow. Keep reflow zone balanced. Avoid routing copper pours touching pads without thermal relief ties.
Place heavy connectors and switch boots in the assembly drawing with torque specs. Call out thread-lock, press-fit force, and insertion direction. Missing mechanical callouts are the #1 cause of NPI delays.
Going from 2→4 layers doubles PCB cost. Going 4→6 adds ~50%. Audit your stack-up: can a high-speed design be routed on 4 layers with strict impedance? Often yes. Every layer removed saves money at scale.
NRE (setup) costs are fixed: stencil (~$150), programming (~$200), test fixture ($500–5000). At 50 units, NRE dominates. At 1000+, unit cost is what matters. Request pricing at 50 / 500 / 5000 to understand your cost curve.
Check LCSC/Digi-Key stock at schematic stage. A single 52-week lead-time part (FPGA, RF module) can delay your entire order. Design in second-source alternates from day one — document in BOM "approved manufacturers" column.
HASL is cheapest but uneven. ENIG adds ~$0.50–2.00/board but gives flat, solderable surfaces. Immersion Silver is excellent for high-frequency RF. Hard gold for edge connectors only. Match finish to function, not default.
Using one CM for bare PCB + assembly (turnkey) eliminates freight, scheduling risk, and finger-pointing on defects. A CM who also does mechanical enclosures enables true box-build pricing, often 15–25% cheaper than managing two vendors.
An engineering change order (ECO) after stencils are cut costs $200–600 in re-tooling. After components are kitted, a BOM change can waste $500–5000 in obsolete inventory. Invest in design reviews before release.
Place ≥ 1mm diameter test pads for ICT probing. Minimum grid pitch: 2.54mm for standard fixtures, 1.27mm for fine-pitch. Keep test pads on one side where possible. Label in silkscreen — saves fixture build time.
Flying probe: low NRE (~$200), slow (1–5 sec/node), ideal for prototypes. Bed-of-nails fixture: $2,000–10,000 NRE, covers 100% nodes in seconds, required above ~500 units. Plan your test strategy at schematic stage.
Add JTAG test access ports to complex digital designs. Boundary scan reaches nets inaccessible to bed-of-nails (BGA under-side). Include a dedicated JTAG header — 5 pins, 2.54mm pitch. Document in test plan.
Design a hardware-in-the-loop (HIL) test spec before manufacturing. Define: power-on sequence, GPIO stimulus/response, comm interfaces (UART/SPI/I2C loopback), RF power output, ADC calibration. A clear test spec cuts debug time by 60%.
Expose SWD, JTAG, or UART bootloader headers for in-system programming. Coordinate with CM on programmer hardware (J-Link, OpenOCD, custom). Budget 10–30 seconds per board for firmware flashing in your cycle time.
Supply the CM with 2–3 verified golden units. These become the functional baseline for first-article inspection and ongoing production correlation. Document all known-good measurements and waveforms in your acceptance test plan.
Choose the right process — or combination — for your product's requirements.
| Technology | Component Types | Min Pitch | Cost/Unit | Speed | Best For | IPC Std |
|---|---|---|---|---|---|---|
| SMT (Surface Mount) | 0201, 0402, QFP, BGA, LGA, QFN | 0.3mm | Low | Very High | High-density, consumer electronics, IoT | IPC-7711/7721 |
| THT (Through-Hole) | Axial, Radial, DIP, TO-92/220 | 0.8mm | Medium | Medium | Power supplies, high-reliability, connectors | IPC-A-610 |
| Mixed Technology | SMT + THT on same board | 0.3mm | Medium+ | Medium | Industrial controls, automotive sub-assemblies | IPC-A-610 C2/C3 |
| BGA / Flip-Chip | BGA, CSP, flip-chip, µBGA | 0.4mm CSP | High | High | RF, processors, memory, high I/O | IPC-7095 |
| Press-Fit | Backplane connectors, power modules | 2.54mm | Variable | Medium | Telecom, servers, connectors requiring no solder | IPC-7525 |
| Selective Solder | THT on mixed-tech boards | 1.0mm | Medium | Lower | Mixed boards where wave solder risks SMT parts | J-STD-001 |
| Conformal Coating | Post-assembly on any technology | — | +$0.10–1.50 | Adds cycle time | Automotive, outdoor, marine, industrial | IPC-CC-830 |
Get a rough budgetary estimate. Actual pricing requires a formal RFQ from your CM.
⚠ Indicative estimates only. Does not include BOM component cost, PCB bare board, freight, or taxes. Always request a formal quote.
Eight critical dimensions to evaluate before committing your production to any CM.
Standards your contract manufacturer should know — and you should reference in your purchase orders.
Use this interactive checklist before sending your design to a contract manufacturer. Tick each item — aim for 100%.
Common questions from engineers and startups evaluating contract electronic assembly.
At minimum: Gerber files (all layers), Excellon drill files, a centroid/XY placement file, and a BOM with MPNs. For quoting, most CMs also want an assembly drawing showing component placement, any special instructions, and your IPC class requirement. The more complete your package, the faster and more accurate the quote.
Prototype pricing is dominated by fixed NRE costs (stencil, programming, setup) spread over very few boards — often $500–2,000+ just in setup. Production pricing amortizes those costs across large volumes, where assembly labor per board (not setup) becomes the main driver. Always request pricing at 3–5 volume breakpoints to understand your full cost model.
For prototypes and early iterations: domestic or near-shore CMs are worth the premium — faster turnarounds (3–5 days vs 3–4 weeks), easier communication, and quicker DFM iteration loops. Once your design is stable and volumes exceed ~500 units/order, offshore CMs with good quality systems (ISO 9001, IPC-A-610 Class 2) typically offer 40–60% lower assembly cost. Run the math at your expected ramp volume before deciding.
The top issues we see: (1) Missing or mis-located fiducial marks; (2) Insufficient pad/courtyard clearances causing pick-and-place nozzle collisions; (3) BOM parts not matching footprint land patterns; (4) No panelization specification; (5) Ambiguous polarity on electrolytic caps or diodes; (6) Via-in-pad without fill/planarization spec; (7) Silkscreen overlapping pads. Running DFM review software (e.g. Valor, Mentor HyperLynx DFM) before submission catches 80% of these.
Request their ISO 9001 and IPC-A-610 certification docs. Ask for a factory visit or video walkthrough. Request first-article photos (solder paste SPI images, post-reflow AOI screenshots, X-ray if BGA) from an existing customer's program (anonymized). Check their DPPM rate and ask how they handle defects found in field returns. Talk to 2–3 reference customers in similar industries. A legitimate CM will welcome this scrutiny.
NRE (Non-Recurring Engineering) covers one-time costs: laser stencil fabrication ($80–250), programming/fixturing ($100–500), and engineering setup time. It's partially negotiable — CMs may waive stencil cost at higher volumes or longer-term agreements. Always clarify: does the NRE cover all future re-runs, or is there a per-run setup fee? Own your tooling (stencil, fixtures) in the contract so you can switch CMs without losing assets.
Yes — many CMs offer full turnkey: bare PCB fabrication + component sourcing + assembly + test. This simplifies logistics, eliminates freight between PCB fab and CM, and creates a single point of accountability for quality. The trade-off is less flexibility in choosing your PCB fab for specific requirements (e.g., tight impedance tolerance or specialty materials like Rogers). Always confirm the CM's PCB fab partner and their capability specs before committing.